The present invention relates to a pipeline analog-to-digital converter comprising a plurality of analog-to-digital converters, each for 1.5 bits (hereinafter referred to as an ADC), connected in series.
FIGS. 1 to 3 are block diagrams broadly showing a conventional pipeline ADC, respectively.
As shown in FIG. 1 illustrating a general configuration, this pipeline ADC has a sample-hold-amplifier (hereinafter referred to as an SHA) for sampling and holding an analog input signal A1 in a predetermined cycle on the basis of a timing signal TM. Series-connected analog-to-digital conversion stages each for 1.5 bits (hereinafter referred to as an STG), namely, STGs 21 to 2m are connected to the output side of the SHA 1.
The respective STGs 21 to 2m, as shown in FIG. 2 illustrating the configuration thereof, comprise a sub-ADC ((hereinafter referred to as an SADC) 3, a sub-digital-to-analog converter ((hereinafter referred to as an SDAC) 4, a subtracter 5, and an SHA 6 with a voltage amplification factor set at 2. The SADC 3 is for comparing an input voltage. V1 with reference voltages xc2x1VR/4, and detecting which of three voltage ranges, namely, a voltage range below xe2x88x92VR/4, a voltage range of from xe2x88x92VR/4 to +VR/4, and a voltage range above +VR/4, the input voltage V1 falls in. Respective signals A, B, C, of 1.5 bits, indicating the result of such detection, are delivered to the SDAC 4. The SDAC 4 outputs voltages xe2x88x92VR/2, 0, +VR/2 in accordance with the signals A, B, C, respectively. The output side of the SDAC 4 is connected to the negative input terminal of the subtracter 5, and the input voltage V1 is connected to the positive input terminal of the subtracter 5. The subtracter 5 is for subtracting an output voltage of the SDAC 4 from the input voltage V1 to thereby deliver a difference in voltage to the SHA 6.
The SHA 6 amplifies the difference in voltage, delivered from the subtracter 5, by a factor of two, and holds an amplified voltage, thereby outputting the amplified voltage as an output voltage VO.
Connected to the output side of the STG 2m in the final stage is an SADC 7 for converting a voltage outputted from the STG 2m into a digital signal of 2 bits. The signals A, B, C, representing the result of the detection by the respective STGs 21 to 2m, and the digital signal D outputted from the SADC 7 after conversion are delivered to an encoder 8. Further, the timing signal TM generated by a timing generator 9 is delivered to the SHA 1, the STGs 21 to 2m, the SADC 7, and the encoder 8.
The encoder 8 sequentially shifts and holds the signals A, B, C, representing the result of the detection, outputted from the respective STGs 21 to 2m, on the basis of the timing signal TM, executing pipeline processing of the respective detection results of the STGs 21 to 2m against the analog input signal A1, correspondingly to the digital signal D outputted from the SADC 7, to thereby generate and output a digital signal DO.
FIG. 3 is an input/output characteristic diagram showing operation of the respective STGs 21 to 2m. The operation thereof is described hereinafter with reference to FIG. 3.
The analog input signal A1 is sampled on the basis of the timing signal TM, and held by the SHA 1. The signal as held is delivered as the input voltage V1 to the STGs 21 in the initial stage, whereupon the SADC 3 of the STGs 21 compares the input voltage V1 with the reference voltages xc2x1VR/4, to thereby make determination. The result of the determination is outputted by rendering any one of the signals A, B, C to represent xe2x80x9c1xe2x80x9d.
If the input voltage V1 is below xe2x88x92VR/4, the signal A representing the result of the determination by the SADC 3 is turned into xe2x80x9c1xe2x80x9d while the signals B, C are turned into xe2x80x9c0xe2x80x9d, respectively. If the input voltage V1 is in the range of from xe2x88x92VR/4 to +VR/4, the signal B is turned into xe2x80x9c1xe2x80x9d while the signals A, C are turned into xe2x80x9c0xe2x80x9d, respectively, and if the input voltage V1 is above +VR/4, the signals A, B are turned into xe2x80x9c0xe2x80x9d, respectively, while the signal C is turned into xe2x80x9c1xe2x80x9d. Those signals A, B, C are delivered to the SDAC 4.
At the SDAC 4, when the signal A is xe2x80x9c1xe2x80x9d, xe2x88x92VR/2 is outputted as the reference voltage, and when the signals B, C are xe2x80x9c1xe2x80x9d, respectively, 0, +VR/2 are outputted as the reference voltages, respectively. The reference voltage outputted from the SDAC 4 is delivered to the subtracter 5 where the reference voltage is subtracted from the input voltage V1. A voltage outputted from the subtracter 5 is held by the SHA 6 on the basis of the timing signal TM and amplified by a factor of two before being delivered as the output voltage VO.
Thus, as shown in FIG. 3, if the input voltage V1 of the STG 21 is in the voltage range below xe2x88x92VR/4, the output voltage VO thereof falls in a voltage range of from xe2x88x92VR to +VR/2. Further, if the input voltage V1 is in the voltage range of from xe2x88x92VR/4 to +VR/4, the output voltage VO thereof falls in a voltage range of from xe2x88x92VR/2 to +VR/2, and if the input voltage V1 is in the voltage range above +VR/4, the output voltage VO falls in a voltage range of from xe2x88x92VR/2 to +VR. The output voltage VO of the STG 21 is delivered as an input voltage V1 to STG 22 in the next stage.
In this way, the respective digital signals of 1.5 bits are outputted from the respective STGs 21 to 2m, on the basis of the timing signal TM, and pipeline processing of those digital signals is executed by the encoder 8, thereby generating the digital signal DO of a predetermined bits.
With the conventional pipeline ADC, however, the following problems have been encountered. That is, since the output voltage VO of each of the STGs 2 is delivered as an input voltage V1 to the STG 2 in the next stage, strict linearity is required of the SHA 6 of the respective STGs 2 such that the output voltage is directly proportional to the input voltage. This is because in the case of poor linearity, an accurate digital value cannot be obtained due to nonlinear distortion at the time of amplification.
Meanwhile, the output voltage VO outputted from the respective STGs 21 to 2m ranges from xe2x88x92VR to +VR, and the input voltage to the SHA 6, corresponding thereto, ranges from xe2x88x92VR/2 to +VR/2. Accordingly, accurate linearity against a wide range of the input voltage is required of the respective SHAs 6. Furthermore, a higher conversion speed is required of the respective SHAs 6. However, high accuracy and high speed being factors required of an amplifier, contradictory to each other, it is not possible to maximize both the factors at the same time. For this reason, with the conventional configuration as shown in FIG. 1, it has been impossible to provide the pipeline ADC simultaneously meeting requirements for high accuracy and high speed.
To solve the problems described as above, in accordance with a first aspect of the invention, there is provided a pipeline ADC for obtaining a digital output signal of a predetermined bits, corresponding to an analog input signal as the target for conversion, by executing pipeline processing based on a clock signal, said pipeline analog-to-digital converter comprising a plurality of STGs connected in series, each comprising an SADC for converting an analog input voltage into a digital signal of 1.5 bits, an SDAC for converting the digital signal into an analog voltage, and an amplifier for sampling and holding a difference in voltage between the input voltage and the analog voltage and amplifying the difference in voltage as held, wherein the STG to which the analog input signal is delivered, in the initial stage of said plurality of the STGs, has the following configuration.
That is, the STG in the initial stage comprises a first amplifier for sampling and holding the analog input signal to thereby output a voltage equivalent to 1/N (provided that N is either 2 or 3) of the analog input signal as a first analog voltage, a first SADC for converting the first analog voltage into a first digital signal of 1.5 bits, a first SDAC for converting the first digital signal into a second analog voltage, a second amplifier for sampling and holding a difference in voltage between the first and second analog voltages, and amplifying the difference in voltage as held by a factor of N to thereby output a third analog voltage.
Said STG further comprises a second SADC for converting the third analog voltage into a second digital signal of 1.5 bits, a second SDAC for converting the second digital signal into a fourth analog voltage, a third amplifier for sampling and holding a difference in voltage between the third and fourth analog voltages, and amplifying the difference in voltage as held by a factor of two to be thereby delivered to the STG in the next stage, and a discriminator for generating a digital signal of 1.5 bits, corresponding to the most significant bit, on the basis of the first and second digital signals.
In the first aspect of the invention, since the pipeline ADC is made up as described above, the STG in the initial stage operates as follows; the analog input signal is sampled and held by the first amplifier, and the voltage equivalent to 1/N of the analog input signal is outputted as the first analog voltage. The first analog voltage is converted into the first digital signal of 1.5 bits by the first SADC, and further, the first digital signal is converted into the second analog voltage by the first SDAC. The first and second analog voltages are delivered to the second amplifier and a difference in voltage therebetween is sampled and held to be further amplified by a factor of N, thereby being outputted as the third analog voltage.
The third analog voltage is converted into the second digital signal of 1.5 bits by the second SADC, and further, the second digital signal is converted into the fourth analog voltage by the second SDAC. The third and fourth analog voltages are delivered to the third amplifier, and a difference in voltage therebetween is sampled and held to be further amplified by a factor of two, thereby being delivered to the STG in the next stage. Meanwhile, the discriminator generates the digital signal of 1.5 bits, corresponding to the most significant bit, on the basis of the first and second digital signals.
Due to such a configuration as described above, the range of the analog voltage delivered to the respective amplifiers is reduced to xc2xd of that for the conventional case, so that requirements for high accuracy and high speed can be simultaneously met.
The invention provides in its second aspect a pipeline ADC similar to that in its first aspect, comprising a STG in the initial stage, having the following configuration.
More specifically, said STG in the initial stage comprises a first holder for holding and outputting a voltage obtained by adding a reference voltage to an analog input signal, a second holder for holding and outputting the analog input signal, a third holder for holding and outputting a voltage obtained by subtracting the reference voltage from the analog input signal, a first sub-A/D converter for comparing the analog input signal with a voltage equivalent to xc2x1xc2xd of the reference voltage to thereby convert the analog input signal into a first digital signal of 1.5 bits, selectors for selecting a voltage outputted from any one of the first, the second, and the third holder, in accordance with the first digital signal, to thereby output as a first analog voltage.
The STG in the initial stage further comprises a second sub-A/D converter for converting the first analog voltage into a second digital signal of 1.5 bits, a sub-D/A converter for converting the second digital signal into a second analog voltage, an amplifier for sampling and holding a difference in voltage between the first and second analog voltages, and amplifying the difference in voltage as held by a factor of two so as to be delivered to the STG in the next stage, and a discriminator for generating a digital signal of 1.5 bits, corresponding to the most significant bit, on the basis of the first and second digital signals.